When an I/O device (Input/Output device) such as a disk device or a network interface performs a data transfer, or packet transmission, for example, a processor in a computer passes a descriptor to an I/O controller which controls the I/O device. The descriptor may include information indicating a kind of a process to be performed by the I/O device, an address of a main memory that is a target of the data transfer and the like. The I/O controller may cause the I/O device to perform an indicated process, based on the information in the descriptor passed from the processor.
In transferring the descriptor to the I/O controller, the processor writes the descriptor to a descriptor storage unit provided in the I/O controller, and transfer the descriptor written to the descriptor storage unit, to the I/O controller. The descriptor storage unit may be a memory unit that is provided separately from the main memory and which can be accessed faster than memory accesses. In addition, the I/O controller may receive a request from the processor, and read the descriptor stored in the main memory.
A data transfer in which a DMA controller sequentially processes a plurality of transfer descriptors included in a TD chain written to a TD chain storage unit by a CPU, and a series of the data transfers between the main memory and the I/O device by direct memory access is proposed.
Conventionally, a processor writes the descriptor to the descriptor storage unit provided in the I/O controller, and then transfers the written descriptor to the I/O controller, latency of transferring the descriptor can be reduced. However, in this method, the I/O controller needs to be provided with the descriptor storage unit having a relatively large capacity.
Moreover, in a method in which the I/O controller receives the request from the processor, and reads the descriptor stored in the main memory, time is required to read the descriptor from the main memory, and thus the latency of transferring the descriptor is increased.
An problem to be addressed is to reduce the latency of transferring the descriptor without increasing a capacity of the memory unit for storing the descriptor.